一、题目要求：

二、硬件电路

三、chat给出的代码

作业三：

仅使用2位数码管，另外2位要熄灭，点亮的2位依次显示00到99，计数器递增频率为2Hz。
VHDL版代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SevenSegmentCounter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           seg_out : out STD_LOGIC_VECTOR(6 downto 0));
end SevenSegmentCounter;

architecture Behavioral of SevenSegmentCounter is
    signal counter : INTEGER range 0 to 99 := 0;
    signal display : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= 0;
        elsif rising_edge(clk) then
            if counter = 99 then
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    process(counter)
    begin
        case counter is
            when 0 => display <= "0000001"; -- 显示 00
            when 1 => display <= "1001111"; -- 显示 01
            -- ... 继续添加其他数字的显示模式
            when 99 => display <= "1001010"; -- 显示 99
            when others => display <= "0000000"; -- 默认熄灭
        end case;
    end process;

    seg_out <= display;

end Behavioral;

 第二版

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TwoDigitCounter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           seg_out : out STD_LOGIC_VECTOR(6 downto 0));
end TwoDigitCounter;

architecture Behavioral of TwoDigitCounter is
    signal counter : INTEGER range 0 to 99 := 0;
    signal display : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
    signal clk_1Hz : STD_LOGIC;

    constant CLOCK_FREQ : INTEGER := 50000000; -- 假设时钟频率为50MHz
    constant COUNT_FREQ : INTEGER := 2; -- 计数器递增频率为2Hz

begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= 0;
        elsif rising_edge(clk) then
            if counter = 99 then
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    process(clk)
    variable prescaler : INTEGER range 0 to CLOCK_FREQ / (2 * COUNT_FREQ) - 1 := 0;
    begin
        if rising_edge(clk) then
            if prescaler = CLOCK_FREQ / (2 * COUNT_FREQ) - 1 then
                prescaler := 0;
                if counter <= 9 then
                    display <= "000" & std_logic_vector(to_unsigned(counter, 4));
                else
                    display <= std_logic_vector(to_unsigned(counter, 7));
                end if;
            else
                prescaler := prescaler + 1;
            end if;
        end if;
    end process;

    seg_out <= display;

end Behavioral;

Verilog语言版 

module SevenSegmentCounter(
    input clk,
    input reset,
    output reg [6:0] seg_out
);

reg [6:0] display;
reg [6:0] segment_pattern [0:99];

integer counter;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        counter <= 0;
    end else begin
        if (counter == 99) begin
            counter <= 0;
        end else begin
            counter <= counter + 1;
        end
    end
end

always @(counter) begin
    case (counter)
        0: display <= 7'b0000001; // 显示 00
        1: display <= 7'b1001111; // 显示 01
        // ... 继续添加其他数字的显示模式
        99: display <= 7'b1001010; // 显示 99
        default: display <= 7'b0000000; // 默认熄灭
    endcase
end

assign seg_out = display;

endmodule

第二版

module TwoDigitCounter(
    input clk,
    input reset,
    output reg [6:0] seg_out
);

reg [6:0] display;
reg [6:0] counter;
reg [27:0] prescaler;

parameter CLOCK_FREQ = 50000000; // 假设时钟频率为50MHz
parameter COUNT_FREQ = 2; // 计数器递增频率为2Hz

always @(posedge clk or posedge reset) begin
    if (reset) begin
        counter <= 7'b0000000;
        prescaler <= 28'b0;
    end else begin
        if (prescaler == (CLOCK_FREQ / (2 * COUNT_FREQ)) - 1) begin
            prescaler <= 28'b0;
            if (counter == 7'b1001001) begin
                counter <= 7'b0000000;
            end else begin
                counter <= counter + 1;
            end
        end else begin
            prescaler <= prescaler + 1;
        end
    end
end

always @(counter) begin
    if (counter <= 7'b1001) begin
        display <= {3'b000, counter};
    end else begin
        display <= counter;
    end
end

assign seg_out = display;

endmodule

 

作业四：

《数码管动态显示 》VHDL、Verilog

仅使用 2 位数码管，另外 2 位要熄灭，点亮的 2 位依次显示 00 到 19，两个按键，第一个按键每按一下数值加 1，第二个按键每按一 下数值减 1。

Verilog版本：

module TwoDigitCounter(
    input clk,
    input reset,
    input btn_increment,
    input btn_decrement,
    output reg [6:0] seg_out
);

reg [6:0] display;
reg [4:0] counter;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        counter <= 5'b00000;
    end else begin
        // 检测增加按钮
        if (btn_increment) begin
            if (counter == 5'b10011) begin
                counter <= 5'b00000; // 循环回零
            end else begin
                counter <= counter + 1;
            end
        end
        // 检测减少按钮
        else if (btn_decrement) begin
            if (counter == 5'b00000) begin
                counter <= 5'b10011; // 循环到 19
            end else begin
                counter <= counter - 1;
            end
        end
    end
end

always @(counter) begin
    // 将计数值转换为数码管的显示模式
    case (counter)
        5'b00000: display <= 7'b0000001; // 显示 00
        5'b00001: display <= 7'b1001111; // 显示 01
        5'b00010: display <= 7'b0010010; // 显示 02
        5'b00011: display <= 7'b0000110; // 显示 03
        5'b00100: display <= 7'b1001100; // 显示 04
        5'b00101: display <= 7'b0100100; // 显示 05
        5'b00110: display <= 7'b0100000; // 显示 06
        5'b00111: display <= 7'b0001111; // 显示 07
        5'b01000: display <= 7'b0000000; // 显示 08
        5'b01001: display <= 7'b0000100; // 显示 09
        5'b01010: display <= 7'b0001000; // 显示 10
        5'b01011: display <= 7'b1100000; // 显示 11
        5'b01100: display <= 7'b0110001; // 显示 12
        5'b01101: display <= 7'b1000010; // 显示 13
        5'b01110: display <= 7'b0100001; // 显示 14
        5'b01111: display <= 7'b0000011; // 显示 15
        5'b10000: display <= 7'b0111001; // 显示 16
        5'b10001: display <= 7'b0101100; // 显示 17
        5'b10010: display <= 7'b0110000; // 显示 18
        5'b10011: display <= 7'b1100011; // 显示 19
        default: display <= 7'b0000000; // 默认熄灭
    endcase
end

assign seg_out = display;

endmodule

 VHDL版本

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TwoDigitCounter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           btn_increment : in STD_LOGIC;
           btn_decrement : in STD_LOGIC;
           seg_out : out STD_LOGIC_VECTOR(6 downto 0));
end TwoDigitCounter;

architecture Behavioral of TwoDigitCounter is
    signal display : STD_LOGIC_VECTOR(6 downto 0);
    signal counter : INTEGER range 0 to 19 := 0;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= 0;
        elsif rising_edge(clk) then
            -- 检测增加按钮
            if btn_increment = '1' then
                if counter = 19 then
                    counter <= 0;  -- 循环回零
                else
                    counter <= counter + 1;
                end if;
            -- 检测减少按钮
            elsif btn_decrement = '1' then
                if counter = 0 then
                    counter <= 19;  -- 循环到 19
                else
                    counter <= counter - 1;
                end if;
            end if;
        end if;
    end process;

    process(counter)
    begin
        case counter is
            when 0 => display <= "0000001"; -- 显示 00
            when 1 => display <= "1001111"; -- 显示 01
            when 2 => display <= "0010010"; -- 显示 02
            when 3 => display <= "0000110"; -- 显示 03
            when 4 => display <= "1001100"; -- 显示 04
            when 5 => display <= "0100100"; -- 显示 05
            when 6 => display <= "0100000"; -- 显示 06
            when 7 => display <= "0001111"; -- 显示 07
            when 8 => display <= "0000000"; -- 显示 08
            when 9 => display <= "0000100"; -- 显示 09
            when 10 => display <= "0001000"; -- 显示 10
            when 11 => display <= "1100000"; -- 显示 11
            when 12 => display <= "0110001"; -- 显示 12
            when 13 => display <= "1000010"; -- 显示 13
            when 14 => display <= "0100001"; -- 显示 14
            when 15 => display <= "0000011"; -- 显示 15
            when 16 => display <= "0111001"; -- 显示 16
            when 17 => display <= "0101100"; -- 显示 17
            when 18 => display <= "0110000"; -- 显示 18
            when 19 => display <= "1100011"; -- 显示 19
            when others => display <= "0000000"; -- 默认熄灭
        end case;
    end process;

    seg_out <= display;

end Behavioral;

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